Dual event command

ABSTRACT

A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No.11/495,418, filed Jul. 28, 2006 now U.S. Pat. No. 7,549,033, which is aContinuation of U.S. application Ser. No. 10/767,555, filed Jan. 29,2004, now issued as U.S. Pat. No. 7,299,329, which are incorporatedherein by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to memory circuits and, in particular, tocircuitry associated with command and address pins of a DRAM (dynamicrandom access memory).

BACKGROUND OF THE INVENTION

In order to perform data transfers, such as a store and an access, toand from conventional DRAM devices, the command and address signals aregenerally initiated on a rising edge (the transition from logic level“zero” to “one”) or alternatively a falling edge of a clock signal. In ahigh speed DRAM design, using the current scheme to store and access thedata from a DRAM can result in requiring a significantly higher numberof command and address pins. Further, any increase in the number ofcommand and address pins, can also result in a significant overhead forthe DRAM controller performing data transfers via multiple DRAMs. Forexample, a DRAM controller coupled to access 8×32DRAMs in a system,parallelly or concurrently, can require nearly 256 bit input/output(I/O) interfaces. Furthermore, for efficient handling of the command andaddress signals, the DRAM controller may also have to assign a similarnumber of command and address pins. Therefore, any increase in thenumber of command and address pins in a DRAM, in the above system, canalso result in requiring similar increase in the command and addresspins in each DRAM for the DRAM controller. This is because of operatingthe command and address signals at half cycles and because of using thecommand and address pins for a single purpose or a single cycle inconventional double data rate (DDR) DRAM devices.

In addition, during the last several decades, memory technology hasprogressed dramatically. The density of commercial memory devices, suchas the DRAM, has increased from 1 Kbit to 256 Mbits per chip, a factorof 256,000. Unfortunately, as the density goes up the number of commandand address pins required to store and access data has also increasedconsiderably. Increasing the number of command and address pins canresult in a bigger package size for reasons described-above. As thepackaging density increases, accommodating more number of command andaddress pins in a smaller package becomes more difficult.

Accordingly, there is a need in the art for a technique to reduce thenumber of command and address pins required in DRAMs to perform datatransfers to and from the DRAMs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a timing diagram illustrating one approach of initiating thecommand and address signals to transfer data to and from the DRAM uponthe rising edge of a clock signal in a conventional DRAM.

FIG. 2 is an exemplary embodiment of a timing diagram illustrating theinitiating of the command and address signals to transfer data to andfrom a DRAM upon the rising and falling edges of a clock signalaccording to the present invention.

FIG. 3 is another exemplary embodiment of a timing diagram illustratingthe initiating of the command and address signals to transfer data toand from a DRAM upon the rising and falling edges of a clock signalaccording to the present invention.

FIG. 4 is another exemplary embodiment of a timing diagram illustratingthe initiating of the command and address signals to transfer data toand from a DRAM upon two substantially consecutive rising edges of aclock signal according to the present invention.

FIG. 5 is another exemplary embodiment of a timing diagram illustratingthe initiating of the command and address signals to transfer data toand from a DRAM upon the two substantially consecutive rising edges of aclock signal according to the present invention.

FIG. 6 is a block diagram illustrating the interconnections between acontroller and multiple DRAMs according to one example embodiment of thepresent invention.

FIG. 7 is a block diagram of an exemplary computer system.

FIG. 8 is a block diagram of an exemplary memory system.

FIG. 9 is an elevational view of a substrate containing semiconductordies.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to variousspecific embodiments in which the invention may be practiced. Theseembodiments are described with sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother embodiments may be employed, and that structural, logical,electrical, and process changes may be made without departing from theteachings of the invention.

In the foregoing description of the preferred embodiments, variousfeatures of the invention are grouped together in a single embodimentfor the purpose of streamlining the disclosure. This method ofdisclosure is not to be interpreted as reflecting an intention that theclaimed invention requires more features than are expressly recited ineach claim. Rather, as the following claims reflect, inventive aspectslie in less than all features of a single disclosed embodiment. Thus,the following claims are hereby incorporated into the description of thepreferred embodiments, with each claim standing on its own as a separatepreferred embodiment of the invention.

The present invention provides techniques to reduce number of commandand address pins required in a DRAM to reduce the package size and toessentially increase the number of command and address signals sent fora given set of command and address pins in the DRAM. The terms “sending”and “initiating” are used interchangeably throughout the document.References to “rising edge” and “falling edge” of a clock or controlsignal is for illustrative purposes only since those skilled in the artreadily know that true or complementary clock and control signals may beused in which a rising edge may be substituted for a falling edge.Therefore, a clock or control signal may substitute any clock transition(rising or falling) and still fall within the scope of this descriptionand claims.

Referring now to FIG. 1, there is illustrated one conventional techniqueemployed in initiating command and address signals by a DRAM controllerto access data from a DRAM upon the rise (active edge) of a timingsignal. As shown in the timing diagram 100 of FIG. 1, the DRAMcontroller sends the command signals 120, such as Chip Select (CS#), RowAddress Strobe (RAS#), Column Address Strobe (CAS#), and Write Enable(WE#) and the address signals 130, such as BA0˜2 and A11˜A0 during arising edge 112 of a clock (CK) signal 110. Also shown in FIG. 1 isclock signal (CK#) 115 which is an inverse of the CK signal 110. It canbe envisioned that the command and address signals can also beinitiated, similarly as described-above, during a falling edge of theCK# signal 115. As described-above, the problem with this technique isas the density of the DRAMs goes up the number of command and addresspins required to store and access data can also increase proportionatelyin each DRAM. Increasing the number of command and address pins canresult in a significantly bigger package size. As the packaging densityincreases, accommodating more number of command and address pins in asmaller package becomes difficult.

Referring now to FIG. 2, there is illustrated an example timing diagram200 of initiating command and address signals by a controller to anintegrated circuit memory device according to the present invention. Asshown in FIG. 2, the command signals 220, such as CS#, RAS#, CAS#, andWE# and address signals 230, such as BA0˜2 and A0˜11 are initiated bythe controller during both rising and falling edges 202 and 204 of atiming cycle of a timing signal 210 to increase the transfer rate of thecommand and address signals during the timing cycle. In someembodiments, the timing cycle of the timing signal is a clock cycle in aclock signal (CK). In these embodiments, the rising and falling edges202 and 204 comprise transition from a logic level “zero” to a logiclevel “one” and transition from the logic level “one” to the logic level“zero”, respectively.

Also in these embodiments, the controller can be a device, such as acentral processing unit (CPU), a graphics processing unit (GPU), aprocessor, and/or a dynamic random access memory (DRAM) controller. Inthese embodiments, the integrated circuit memory device is a DRAMdevice. It can be seen from FIG. 2 that by sending the command andaddress signal upon both the rising and falling edges of a clock cyclethe number of command and address signals sent during a clock cycle canbe significantly more than the conventional technique described-abovewith reference to FIG. 1. It can be envisioned that by increasing thesending of the number of command and address signals in a clock cycle,the number of required command and address pins can be considerablyreduced to achieve a higher packaging density in a DRAM.

The clock signal (CK#) 215 is an inverse of the clock signal (CK) 210shown in FIG. 2. Again, it can be envisioned that by initiating thecommand and address signals during the rising and falling edges ofCK#215, similar to initiating the command and address signals during therising and falling edges of CK 210 as described-above, the transfer rateof the command and address signals 220 and 230 sent during the clockcycle can be increased.

Referring now to FIG. 3, there is illustrated another example timingdiagram 300 of initiating command and address signals by a controller toan integrated circuit memory device according to the present invention.As shown in FIG. 3, the command signals 320, such as CS#, RAS#, CAS#,and WE# and address signals 330, such as BA0˜2 and A12˜8 are initiatedby the controller during a rising edge 302 of a clock cycle of a CK 310.In addition, the address signals, such as A0˜7 are initiated during afalling edge 304 of the clock cycle of the CK 310 to increase thetransfer rate of the command and address signals during the clock cyclefor a given number of command and address pins in a DRAM device. Againit can be envisioned that using an inverse clock signal (CK#) 312 shownin FIG. 3 and initiating command and address signals as described-abovecan also increase the transfer rate of the command and address signals320 and 330 sent by the controller during the clock cycle

Referring now to FIG. 4, there is illustrated an example timing diagram400 of initiating command and address signals by a controller to anintegrated circuit memory device according to the present invention. Asshown in FIG. 4, the command signals 420, such as CS#, RAS#, CAS#, andWE# and address signals 430, such as BA0˜2 and A0˜11 are initiated bythe controller during two substantially consecutive rising edges 402 ofa CK 410 to increase the transfer rate of the command and addresssignals during the two substantially consecutive cycles. The transferrate of the command and address signals achieved by using this method400 is lower than the transfer rate achieved with the method 200described-above with reference to FIG. 2. Because, the method 400essentially requires one additional clock cycle to complete sending allof the command and address signals 420 and 430. But, in the GHz clockfrequency era, adding one additional clock cycle to send the command andaddress signals 420 and 430 does not significantly lower the transferrates.

Referring now to FIG. 5, there is illustrated another example timingdiagram 500 of initiating command and address signals by a controller toan integrated circuit memory device according to the present invention.As shown in FIG. 5, the command signals 520, such as CS#, RAS#, CAS#,and WE# and address signals 530, such as BA0˜2 and A11˜9 are initiatedby the controller during a rising edge 502 of a clock cycle of a CK 510.In addition, the address signals, such as A0˜8 are initiated during arising edge 504 of a substantially subsequent clock cycle of the CK 510to increase the transfer rate of the command and address signals duringtwo substantially subsequent clock cycles for a given number of commandand address pins in an integrated circuit memory device. Again, it canbe envisioned that an inverse of the CK 510 can also be used, asdescribed-above, to increase the transfer rate of the command andaddress signals sent during the clock cycle. Again, it can also be seenthat in the GHz range, adding one additional clock cycle to send theaddress signals 530 does not significantly lower the transfer rates ofthe command and address signals between the controller and one or moreintegrated circuit memory devices. The hatched state shown in FIGS. 1-5for the command and address signals indicate that the signals must beheld in one state so they may be read. The signal portion marked withvertical lines indicate that the signals may be in any state since theyare not being read during that time period.

Referring now to FIG. 6, there is illustrated an example embodiment of amemory circuit 600 according to the present invention. The memorycircuit 600 includes one or more DRAMs 610. Each of the DRAMs 610includes multiple data pins 640 and multiple command and address pins630. The memory circuit 600 further includes a controller 620 coupled tothe one or more DRAMs 610 via the data pins 640 and the command andaddress pins 630. In some embodiments, the controller is a device, suchas a CPU, a GPU, a processor, and a DRAM controller. Also in theseembodiments, the DRAMs can be any integrated circuit memory devices,such as flash memory device, a volatile memory device, a non-volatilememory device, a static random access memory (SRAM) device, and/or astatic memory device. In some embodiments, the multiple command andaddress pins 630 are coupled to the controller 620 through a couplingmedium 650, such as input/output interface and/or a bus.

In operation, the controller 620 sends command and address signals toeach integrated circuit memory device 610 via the associated multiplecommand and address pins 630, respectively, during a clock cycle of aclock signal so as to increase the transfer rate of the command andaddress signals during the clock cycle. This is accomplished by sendinga higher number of command and address signals than available number ofcommand and address pins 630 in each integrated circuit memory device610.

In some embodiments, the controller 620 sends the command and addresssignals upon both rising and falling edges of a clock cycle whentransferring data to and from each integrated circuit memory device 610to increase transfer rate of the command and address signals within theclock cycle for a given number of the command and address pins 630 ineach integrated circuit memory device 610. In other embodiments, thecontroller 620 sends the command and address signals upon a rising edgeof a clock cycle and further sends remaining address signals upon afalling edge of the clock cycle when transferring the data to and fromthe integrated circuit memory device 610.

In some embodiments, the controller 620 sends the command and addresssignals to each integrated circuit memory device 610 via its associatedmultiple command and address pins 630, respectively, upon twosubstantially consecutive rising edges of a clock signal to increasetransfer rate of the command and address signals. In other embodiments,the controller 620 sends the command and address signals to eachintegrated circuit memory device 610 via its associated multiple commandand address pins 630, respectively, upon a rising edge of a clock cyclein a clock signal. Further, the controller 620 sends the address signalsupon a rising edge of a substantially subsequent clock cycle to eachintegrated circuit memory device 610 via its associated multiple commandand address pins 630, respectively, to increase transfer rate of thecommand and address signals to each integrated circuit memory device 610in the two substantially consecutive clock cycles. In the abovedescribed embodiments, each of the integrated circuit memory devices 610perform the memory command in response to receiving the set of commandand address signals. The advantages in using the above techniques tosend command and address signals are described-above in more detail withreference to FIGS. 2-5.

FIG. 7 is a block diagram of a system according to one embodiment of thepresent invention. Computer system 700 contains a processor 710 and amemory system 702 housed in a computer unit 705. Computer system 700 isbut one example of an electronic system containing another electronicsystem, e.g., memory system 702, as a subcomponent. The memory system702 includes a memory device that includes a multichip module asdiscussed in various embodiments of the present invention. Computersystem 700 optionally contains user interface components. These userinterface components include a keyboard 720, a pointing device 730, amonitor 740, a printer 750, and a bulk storage device 760. It will beappreciated that other components are often associated with computersystem 700 such as modems, device driver cards, additional storagedevices, etc. It will further be appreciated that the processor 710 andmemory system 702 of computer system 700 can be incorporated on a singleintegrated circuit. Such single-package processing units reduce thecommunication time between the processor and the memory circuit. Any ofthese components of the system may contain a memory controller toinitiate command and address signals to retrieve data from a memorydevice according to the present invention. This is particularly true ofgraphics subsystem 770 of FIG. 7 utilizing SGRAM that includes a solidfilm formed as discussed in various embodiments of the presentinvention.

FIG. 8 is a block diagram of a system according to one embodiment of thepresent invention. Memory system 800 contains one or more multichipmodules 802 and a memory controller 812. Each memory module 802 includesat least one memory device 810. Memory controller 812 provides andcontrols a bidirectional interface between memory system 800 and anexternal system bus 820. Memory system 800 accepts a command signal fromthe external bus 820 and relays it to the one or more memory modules 802on a command link 830. Memory system 800 provides for data input anddata output between the one or more memory modules 802 and externalsystem bus 820 on data links 840. At least one of the memory devices 810includes the DRAM controller to initiate command and address signals toretrieve data from one or more DRAMs according to the present matter.

With reference to FIG. 9, in one embodiment, a semiconductor die 910 isproduced from a silicon wafer 900. A die is an individual pattern,typically rectangular, on a substrate that contains circuitry to performa specific function. A semiconductor wafer will typically contain arepeated pattern of such dies containing the same functionality. Die 910may contain multichip modules, as discussed above. Die 910 may furthercontain additional circuitry to extend to such complex devices as amonolithic processor with multiple functionality. Die 910 includes aDRAM controller coupled to one or more DRAMs as discussed in variousembodiments of the present invention.

CONCLUSION

The present invention provides techniques to send command and addresssignals on both the rising and falling edges and/or on two consecutiverising or falling edges of a clock cycle (timing signal), therebyessentially reducing the number of command and address pins required bythe DRAMs.

In one aspect, the invention provides techniques for reducing the numberof command and address pins required in a DRAM. In this aspect, theinvention includes sending command and address signals to one or moreDRAMs to transfer data to and from the DRAMs upon both the rising andfalling edges of a clock cycle. In accordance with another aspect of thepresent invention, a technique for reducing the number of command andaddress pins required on a DRAM includes sending the command and addresssignals on the first edge of a clock cycle and further sending addresssignals on the following edge of the clock cycle.

In accordance with yet another aspect of the present invention, atechnique for reducing the number of required command and address pinson a DRAM includes sending the command and address signals on twoconsecutive rising edges (or falling edges) of a clock signal. Inaccordance with yet another aspect of the present invention, a techniquefor reducing the number of required command and address pins on a DRAMincludes sending the command and address signals on a rising edge of aclock cycle and further sending the address signals on a subsequentrising edge of the clock cycle.

Additional advantages and features of the present invention will be moreapparent from the detailed description and accompanying drawings, whichillustrate preferred embodiments of the invention.

The above description illustrates preferred embodiments, which achievethe features and advantages of the present invention. It is not intendedthat the present invention be limited to the illustrated embodiments.Modifications and substitutions to specific process conditions andstructures can be made without departing from the spirit and scope ofthe present invention. Accordingly, the invention is not to beconsidered as being limited by the foregoing description and drawings,but is only limited by the scope of the appended claims.

The invention claimed is:
 1. A method of operating a memory device, themethod comprising: receiving a memory command within a single clockcycle, wherein the memory command includes a command and an address, andwherein the receiving the memory command includes: receiving the commandand a first portion of the address on a number of pins in relation to afirst edge of a clock pulse of the single clock cycle; and receiving asecond portion of the address on the number of pins in relation to asecond edge of the clock pulse, wherein the receiving the second portionof the address includes using at least a portion of the number of pinsused to receive the command, wherein the command includes a plurality ofcommand signals, wherein the address includes a plurality of addresssignals, wherein the sum of the plurality of command signals and theplurality of address signals is greater than the number of pins; andwherein the number of pins used to receive the command includes a pinthat is free from receiving any one of address signals included in thesecond portion of the address.
 2. The method of claim 1, furthercomprising: performing the memory command, in the memory device, inresponse to receiving the command and the address within the singleclock cycle.
 3. The method of claim 1, wherein the operating a memorydevice includes operating a DRAM memory device.
 4. The method of claim1, wherein the first edge includes a rising edge, the rising edgeincluding a transition from logic level “zero” to logic level “one”, andwherein the second edge includes a falling edge, the falling edgeincluding a transition from logic level “one” to logic level “zero”. 5.The method of claim 1, wherein receiving the command and the addressincludes receiving the command and the address from an externalcontroller.
 6. The method of claim 5, wherein the receiving from theexternal controller includes receiving from at least one of a centralprocessing unit (CPU), a graphics processing unit (GPU), or a processor.7. The method of claim 1, wherein the pin, that is free from receivingany one of the address signals included in the second portion of theaddress, is a CS# signal of the command signals.
 8. A method ofoperating a memory controller, the method comprising: sending a memorycommand within a single clock cycle, wherein the memory command includesa command and an address, wherein the command includes a plurality ofcommand signals, wherein the address includes a plurality of firstaddress signals and a plurality of second address signals, and whereinthe sending the memory command includes: sending a plurality of commandsignals to a plurality of first pins of the a memory device, and theplurality of first address signals to a plurality of second pins of thememory device in relation to a first edge of a clock pulse of the sibclock cycle; and sending a first part of the plurality of second addresssignals to a portion of a plurality of first pins of the memory deviceand a second part of the plurality of second address signals to aplurality of second pins of the memory device in relation to a secondedge of the single clock pulse, wherein the plurality of first pins ofthe memory device includes a pin that is free from receiving any one ofthe plurality of second address signals, and wherein the sum of theplurality of command signals and the plurality of first and secondaddress signals is greater than the number of pins.
 9. The method ofclaim 8, further comprising: performing a memory command, in the memorydevice, in response to receiving the command and the address from thememory controller.
 10. The method of claim 8, wherein the first edgeincludes a rising edge, the rising edge including a transition fromlogic level “zero” to logic level “one”, and wherein the second edgeincludes a falling edge, the falling edge including a transition fromlogic level “one” to logic level “zero”.
 11. The method of claim 8,wherein the pin, that is free from receiving any one of the plurality ofsecond address signals, is a CS# signal of the command signals.
 12. Amemory device comprising: a set of first command pins; and a set ofsecond address pins; and wherein the memory device is configured toreceive a first portion of a word in relation to a first edge of a clockpulse of a plurality of clock pulses, wherein the first portion of theword comprises a set of command signals and a first subset of addresssignals, wherein the set of first pins are configured to receive the setof command signals and the set of second pins are configured to receivethe first subset of address signals, wherein the memory device isconfigured to receive a second portion of the word in relation to asecond edge of the clock pulse, wherein the second portion of the wordcomprises a second subset of address signals, wherein the set of firstpins are configured to receive at least a portion of the second subsetof address signals, wherein at least one pin of the set of the firstpins is free from receiving any one of the second subset of addresssignals, and wherein the set of the second pins are configured toreceive a remaining portion of the second subset of address signals; andwherein the memory device is configured to perform a memory command inresponse to receiving the command signals and the address signals withina single clock cycle, the single clock cycle including the first edge ofthe clock pulse and the second edge of the clock pulse.
 13. The memorydevice of claim 12, including a controller configured to send the firstportion of the word in relation to the first edge of the clock pulse andconfigured to send the second portion of the word in relation to thesecond edge of the clock pulse.
 14. The memory device of claim 13,wherein the controller comprises at least one of a central processingunit (CPU), a graphics processing unit (GPU), or a processor.
 15. Themethod of claim 12, wherein at least one of the set of the first pins isa CS# signal of the command signals.
 16. An apparatus comprising: acontroller configured to send a memory command in a single clock cycle,wherein the controller is configured to send a first portion of thememory command in relation to a first edge of the clock cycle, whereinthe first portion of the memory command comprises a set of commandsignals and a first subset of address signals, wherein the controller isconfigured to send the set of command signals to command pins of amemory device and to send the first subset of address signals to addresspins of the memory device, wherein the controller is configured to senda second portion of the memory command in relation to a second edge ofthe clock cycle, wherein the second portion of the memory commandcomprises a second subset of the address signals, and wherein thecontroller is configured to send the second subset of the addresssignals to a portion of the command pins and to the address pins of thememory device, wherein the command pins includes a pin that is free fromreceiving any one of the address signals.
 17. The apparatus of claim 16,wherein the controller includes at least one of a central processingunit (CPU), a graphics processing unit (GPU), or a processor.
 18. Themethod of claim 16, wherein the pin, that is free from receiving any oneof the address signals, is a CS# signal of the command signals.
 19. Amethod of operating a memory device, the method comprising: receiving amemory command within a single clock cycle, wherein the memory commandincludes a command and an address, wherein the command includes aplurality of command signals, wherein the address includes first andsecond portions, and wherein the receiving the memory command includes:receiving the command and the first portion of the address in relationto a first edge of a clock pulse of the single clock cycle; andreceiving the second portion of the address in relation to a second edgeof the clock pulse of the single clock cycle, and wherein the receivingthe second portion of the address is carried out in a condition that atleast one of pins of the memory device, that are used to receive thecommand signals in relation to the first edge of the clock pulse of thesingle clock cycle, is configured to receive information that isirrelevant to the second portion of the address in relation to thesecond edge of the clock pulse of the single clock cycle.
 20. A methodof operating a memory controller, the method comprising: sending amemory command within a single clock cycle, wherein the memory commandincludes a command and an address, wherein the command includes aplurality of command signals, wherein the address includes first andsecond portions, and wherein the sending the memory command includes:sending a memory device the command and the first portion of the addressin relation to a first edge of a clock pulse of the single clock cycle;and sending the memory device the second portion of the address inrelation to a second edge of the clock pulse of the single clock cycle,and wherein the sending the memory device the second portion of theaddress is carried out in a condition that the memory controller isconfigured to provide at least one of the pins of the memory device thatare used to receive the command signals in relation to the first edge ofthe clock pulse of the single clock cycle, with information that isirrelevant to the second portion of the address in relation to thesecond edge of the clock pulse of the single clock cycle.